As semiconductor geometries continue to shrink, manufactures increasingly rely on Transmission electron microscopes (TEMs) for monitoring the process, analyzing defects, and investigating interface layer morphology. Transmission electron microscopes (TEMs) allow observers to see features having sizes on the order of nanometers. In contrast to SEMs, which only image the surface of a material, TEM also allows analysis of the internal structure of a sample. In a TEM, a broad beam impacts the sample and electrons that are transmitted through the sample are focused to form an image of the sample. The sample must be sufficiently thin to allow many of the electrons in the primary beam to travel though the sample and exit on the opposite site.
Because a sample must be very thin for viewing with transmission electron microscopy (whether TEM or STEM), preparation of the sample can be delicate, time-consuming work. The term “TEM” as used herein refers to a TEM or a STEM and references to preparing a sample for a TEM are to be understood to also include preparing a sample for viewing on an STEM. The term “STEM” as used herein also refers to both TEM and STEM.
TEM samples are typically less than 100 nm thick, but for some applications samples must be considerably thinner. With advanced processes at 30 nm and below, the sample needs to be less than 20 nm in thickness in order to avoid overlap among small scale structures. Currently thinning below 30 nm is difficult and not robust. Thickness variations in the sample result in sample bending, overmilling, or other catastrophic defects. For such small samples, preparation is a critical step in TEM analysis that significantly determines the quality of structural characterization and analysis of the smallest and most critical structures.
Even though the information that can be discovered by TEM analysis can be very valuable, the entire process of creating and measuring TEM samples has historically been so labor intensive and time consuming that it has not been practical to use this type of analysis for manufacturing process control. While the use of FIB methods in sample preparation has reduced the time required to prepare samples for TEM analysis down to only a few hours, it is not unusual to analyze 15 to 50 TEM samples from a given wafer. As a result, speed of sample preparation is a very important factor in the use of TEM analysis, especially for semiconductor process control.
A significant problem for the preparation of ultra thin (<30 nm thick) TEM samples is commonly referred to as “curtaining,” in which non-uniform high-density materials on the surface of an integrated circuit produce a non-planar face on the TEM sample after thinning. Top-down thinning of a sample having these types of structural or density variations will cause vertical ridges to propagate from the denser materials (i.e. metal lines) near the top of the sample (the top being defined as closest to the ion beam source) down the face of the cross-section, running in a direction parallel to the ion beam direction. Curtaining is most often observed in semiconductor materials where multiple patterned layers of materials having a low sputtering yield blocks a faster sputtering yield material. Curtaining may also be observed in materials exhibiting different topographic regions where changes in sputtering yields vary with the milling incident angle. Curtaining artifacts reduce the quality of the TEM imaging and limit the minimal useful specimen thickness. For ultra-thin TEM samples, defined herein as samples having a thickness of less than 30 nm, the two cross-section faces are obviously in very close proximity so thickness variations from curtaining effects can cause a sample to be unusable. FIGS. 1A and 1B show photomicrographs of thinned samples showing curtaining on the sample faces.
In order to minimize curtaining in TEM sample preparation, it is known to invert the samples so that the bottom of the sample (the substrate) is facing the FIB column. Because the substrate portion of the sample will not have imbedded features such as metal lines or transistors, curtaining artifacts will not be introduced into the portion of the sample face containing the region of interest, i.e., the layers of circuitry on the top surface of the semiconductor. While this technique works reasonably well for TEM samples having a thickness of 50 to 100 nm, for ultra-thin samples having a sample thickness of 30 nm or less, even samples prepared by inverting the sample before thinning often show milling artifacts resulting in a undesirably non-uniform sample face.
Thus, there is still a need for an improved method of TEM sample preparation to allow the preparation of ultra-thin TEM samples.